1. Field of the Invention
The present invention relates to a power supply. More particularly, the present invention relates to a pulse frequency modulating circuit which may automatically adjust the working period, and a power supply using the pulse frequency modulating circuit, and a method for stabling voltage.
2. Description of Related Art
Power supply is a commonly used product in our daily life, and nearly every electrical product has a power supply for supplying power to the loads such as speakers, electric heaters, screens, lamps and motors etc. In recent years, in the field of power supply, the energy conversion efficiency changes as the load changes, and we hope the power supply may still provide a high efficient and stable power when a system is full loaded or a significant changing of load occurs in a system. On the application level, the electronic products such as processors, random access memories, displays and cell phones etc. are seldom full loaded all the time, especially the mobile communication products such as cell phones are usually in a energy saving mode of on-call state. Thus, a power supply which may provide a high energy conversion efficiency under any state of load is very important.
FIG. 1 is a circuit diagram of a conventional power supply. Referring to FIG. 1, the power supply 100 includes a pulse frequency modulating circuit 170 and a power converting circuit 150 for driving a load 160, wherein the pulse frequency modulating circuit 170 includes a reference voltage generator 110, an amplifier 111, a pulse generating circuit 120, an AND gate 130 and a buffer circuit 140. The boost converter is used as example for the power converting circuit 150.
The operation of the circuit of FIG. 1 is as follows: the amplifier 111 processes a feedback voltage Vfb and a reference voltage Vref generated by the reference voltage generator 110. Since the feedback voltage Vfb is in direct proportion to the output voltage Vout, if the feedback voltage Vfb is greater than the reference voltage Vref, it means the present output voltage Vout is relatively high, and there is no need for pulling up the output voltage Vout through the boost circuit 150. Here the output comparing signal Vcomp of the amplifier 111 is logical low, and thus the AND gate 130 ignores the pulse signal from the pulse generating circuit 120, and outputs a logical low to halt the boost circuit 150. When the output voltage Vout is decreased, and the feedback voltage Vfb is lower than the reference voltage Vref, the output comparing signal Vcomp of the amplifier 111 is logical high, and thus the output signal of the AND-gate 130 is a pulse signal from the pulse generating circuit 120. The pulse signal processed by the buffer circuit 140 increases its driving ability and drives the boost circuit 150 for increasing the output voltage Vout.
In the aforementioned related art, the pulse signal generated by the pulse generating circuit 120 has a fixed enable time. If the enable time is too short, the pulse frequency modulating circuit 170 will spend a long time for pulling up the output voltage Vout through the boost circuit 150. However, if the enable time is too long, though the boost circuit 150 may quickly pull up the output voltage Vout, but more power is wasted on energy conversion, and the efficiency of energy conversion may decrease accordingly, and a low efficiency of energy conversion will cause a significant consumption of power and increase the operation temperature of the product.
Thus, during the production of the pulse frequency modulating circuit 170, some of the manufacturers consider to use a programmable pulse generating circuit 120 with a function of setting the enable time. A system engineer of a manufacture plant, who uses the pulse frequency modulating circuit 170 may adjust enable time through the programmable pulse generating circuit 120 based on different application. Since there are no certain rules for adjusting the enable time, the engineer has to spend a lot of time on experimentation to obtain a preferred enable time according to the application of the product. However, this try and error method will waste a lot of time. If it is lucky enough or the system engineer is experienced, the preferred enable time may be obtained within two or three experimentations, but with a bad luck or an inexperienced engineer, hundreds of experimentations have to be performed for obtaining the preferred enable time. Thus, this try and error method may greatly increase the development costs and delay the delivery time of said product which may cause loss of business opportunities, and the loss may be immeasurable.